1. Field of the Invention
The present invention relates to a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having a scalar processing unit and a plurality of vector processing units forming a vector pipeline.
2. Description of the Related Art
FIG. 9 shows structure of a shared memory type parallel processing system employing a CPU in a conventional vector processing device. In this system, a plurality of CPUs 100a-100n are connected to share one main storage device 200.
Detailed structure of each of the CPUs 100a-100n is shown in FIG. 10. Each of the CPUs 100a-100n includes, as illustrated in the figure, a scalar processing unit 101, an instruction control unit 102, vector processing units 104a-104n and a memory access network unit 105.
An external processing instruction xe2x80x9cEX-RQxe2x80x9d issued from the scalar processing unit 101 is transferred to the instruction control unit 102. The instruction control unit 102 issues a vector processing instruction xe2x80x9cV-RQxe2x80x9d through the management of resources of the vector processing units 104a-104n existing only in its own CPU.
Therefore, structure of the scalar processing unit 101 and a vector pipeline in each of the CPUs 100a-100n is always constant and can not be changed.
Examples of conventional vector processing devices are disclosed, for example, in Japanese Patent Laying-Open (Kokai) No. Showa 63-127368 and Japanese Patent Laying-Open (Kokai) No. Showa 63-10263. In either of the vector processing devices disclosed in the literature, structure of a scalar processing unit and a vector pipeline is fixed and fails to allow the number of vector pipelines accompanying the scalar processing unit to be flexibly modified according to purposes.
The above-described conventional vector processing device have the following problems.
The first problem is that while a vectorization rate and the like varies according to an application to run, an appropriate vector processing resource can not be assigned thereto.
The reason is that since the number of vector pipelines at each CPU is constant at any time, when an application with a vectorization rate lower than expected runs, surplus of vector resources is caused. By contraries, when an application with a higher vectorization rate or longer vector length runs, vector pipelines whose structure is fixed in advance limits the upper bound of vector processing performance to prevent further improvement of processing performance.
The second problem is that even when an integration degree of Large Scale Integrated Circuits, LSIs, is increased, still remains the necessity of developing a scalar processing unit and vector pipe line as separate LSIs.
The reason is that although higher integration of LSIs enables a scalar processing unit and approximately one vector pipeline to be made into one chip, because conventional multi-vector pipeline structure does not allow the use of a scalar processing unit existing in each LSI at the time of connecting a plurality of such LSIs, the volume of hardware will be wastefully used, resulting in developing a scalar processing unit and a vector pipeline as separate LSIs as is conventionally done. This method, however, involves many factors contributing to cost increase, such as an increase in the number of LSI development processes, an increase in the number of kinds of LSI developments and a reduction in the number of products of each kind of LSI.
An object of the present invention is to provide a vector processing system which allows the number of vector pipelines accompanying a scalar processing unit to be changed flexibly according to purposes.
Another object of the present invention is to provide a vector processing system which operates as if it shared a single vector pipeline from a scalar processing unit of each independent processor.
According to the first aspect of the invention, a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, wherein
the CPUs are divisionally set to be a master CPU and a plurality of slave CPUs, and
the vector processing means of the plurality of slave CPUs are operated as a multi-vector pipeline accompanying the scalar processing of the master CPU.
According to the second aspect of the invention, a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means,
wherein the vector processing means of the plurality of CPUs are all regarded as a single multi-vector pipeline to operate as if each scalar processing means of each the CPU shared the single multi-vector pipeline.
According to the third aspect of the invention, a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, wherein
the CPUs are connected to each other by a path for transferring a vector processing instruction generated from each the CPU to each CPU, and
each the CPU comprises:
issuing means for issuing a vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through the path, and
vector processing instruction control means for comparing the issuing source CPU information contained in the vector processing instruction transferred and structure information regarding a vector pipeline of its own CPU to determine contents of processing for the vector processing instruction transferred.
According to the fourth aspect of the invention, a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, wherein
the CPUs are connected to each other by a path for transferring a vector processing instruction generated from each the CPU to each CPU,
the CPUs are divisionally set to be a master CPU for executing scalar processing, as well as issuing a vector processing instruction to other CPU and a slave CPU for receiving a vector processing instruction transferred from the master CPU to operate as a multi-vector pipeline in synchronization with the vector processing unit in the master CPU,
the master CPU comprises
issuing means for issuing the vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through the path, and
the master CPU and the slave CPU comprises
vector processing instruction control means for comparing the issuing source CPU information contained in the vector processing instruction transferred and master CPU information set at its own CPU to issue, to the vector processing means, an instruction based on the vector processing instruction transferred when the information accord with each other and invalidate the vector processing instruction when the information disaccord with each other.
In the preferred construction, the vector processing instruction control means of the master CPU and the slave CPU comprise
extraction means for separating the vector processing instruction transferred into a main body of the vector processing instruction and the issuing source CPU information and outputting the instruction and information,
comparison means for comparing the issuing source CPU information separated and the master CPU information set at its own CPU,
invalidation processing means for storing the vector processing instruction from the extraction means into an instruction stack when a comparison by the comparison means results in finding accord, and invalidating the vector processing instruction when the comparison results in finding disaccord, and
instruction issuing processing means for issuing an instruction based on the vector processing instruction stored in the instruction stack to the vector processing means according to re source conditions of the vector processing unit.
In another preferred construction, the vector processing instruction control means of the master CPU and the slave CPU comprise
an instruct ion stack for storing the vector processing instruction transferred, and
instruction issuing processing means for comparing the issuing source CPU information contained in the vector processing instruction stored in the instruction stack and master CPU information set at its own CPU and when a comparison results in finding accord, issuing an instruction based on the vector processing instruction to the vector processing means and when the comparison results in finding disaccord, refraining from issuing an instruction based on the vector processing instruction to release the relevant area of the instruction stack, and
in the instruction stack, the vector processing instruction is stored with the issuing source CPU information contained.
In another preferred construction, the vector processing instruction control means of the master CPU and the slave CPU comprise
stopping means for stopping operation of the scalar processing means of its own CPU when its own CPU is a slave CPU, the stopping means including:
storage means for storing master CPU information indicative of a CPU functioning as a master CPU for its own CPU and CPU information of its own CPU, and
comparison means for comparing master CPU information and its own CPU information stored in the storage means when the vector processing instruction is transferred and outputting an operation stop signal of the scalar processing means of its own CPU when the comparison results in finding disaccord.
According to the fifth aspect of the invention, a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, wherein
the CPUs are connected to each other by a path for transferring a vector processing instruction generated from each the CPU to each CPU, and
each the CPU comprises:
issuing means for issuing a vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through the path, and
vector processing instruction control means for storing the vector processing instruction transferred in a plurality of instruction stacks corresponding to the respective CPUs based on the issuing source CPU information to control instruction issuance based on the
vector processing instruction according to priority of each of the plurality of instruction stacks and resource information of the vector processing means.
In the preferred construction, the vector processing instruction control means of each the CPU comprises
a plurality of instruction stacks corresponding to the respective CPUs,
instruction issuing source detection means for detecting the issuing source CPU information contained in the vector processing instruction transferred and storing the vector processing instruction in the instruction stack corresponding to the information,
arbitration means for determining, for each of the plurality of instruction stacks, instruction issuance based on a vector processing instruction from which instruction stack the priority is to be given to, and
instruction issuing processing means for issuing an instruction based on the vector processing instruction to the vector processing means according to the contents determined by the arbitration means and resource information of the vector processing means.
According to the sixth aspect of the invention, a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, comprising the steps of:
at each the CPU
issuing a vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through a path connecting the CPUs to each other, and
comparing the issuing source CPU information contained in the vector processing instruction transferred and structure information regarding a vector pipeline of its own CPU to determine contents of processing for the vector processing instruction transferred.
According to the seventh aspect of the invention, a method of controlling a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, comprising the steps of:
divisionally setting the CPUs to be a master CPU for executing scalar processing, as well as issuing a vector processing instruction to other CPU and a slave CPU for receiving a vector processing instruction transferred from the master CPU to operate as a multi-vector pipeline in synchronization with a vector processing unit in the master CPU,
at the master CPU,
issuing the vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through a path connecting the CPUs to each other, and
at the master CPU and the slave CPU
comparing the issuing source CPU information contained in the vector processing instruction transferred and master CPU information set at its own CPU, and
issuing, to the vector processing means, an instruction based on the vector processing instruction transferred when a comparison results in finding accord and invalidating the vector processing instruction when the comparison results in finding disaccord.
In the preferred construction, the method of controlling a shared memory type vector processing system further comprising the steps of
at the master CPU and the slave CPU comparing the issuing source CPU information contained in the vector processing instruction transferred and master CPU information set at its own CPU,
storing the vector processing instruction in an instruction stack when a comparison results in finding accord and invalidating the vector processing instruction when the comparison results in finding disaccord, and
issuing an instruction based on the vector processing instruction stored in the instruction stack to the vector processing means according to resource conditions of the vector processing means, and
at the master CPU and the slave CPU
comparing the issuing source CPU information contained in the vector processing instruction stored in the instruction stack and master CPU information set at its own CPU, and
issuing an instruction based on the vector processing instruction to the vector processing means when a comparison results in finding accord and refraining from issuing an instruction based on the vector processing instruction to release a relevant area of the instruction stack when a comparison results in finding disaccord.
In another preferred construction, the method of controlling a shared memory type vector processing system further comprising the step of
stopping operation of the scalar processing means of its own CPU when its own CPU is a slave CPU.
According to the eighth aspect of the invention, a method of controlling a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, comprising the steps of:
connecting the CPUs to each other by a path for transferring a vector processing instruction generated from each the CPU to each CPU, and
at each the CPU
issuing a vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through the path, and
storing the vector processing instruction transferred in a plurality of instruction stacks corresponding to the respective CPUs based on the issuing source CPU information to control instruction issuance based on the vector processing instruction according to priority of each of the plurality of instruction stacks and resource information of the vector processing means.
In the preferred construction, the method of controlling a shared memory type vector processing system further comprising the steps of:
at each the CPU
detecting the issuing source CPU information contained in the vector processing instruction transferred and storing the vector processing instruction in the instruction stack corresponding to the information,
determining, for each of the plurality of instruction stacks, instruction issuance based on a vector processing instruction from which instruction stack the priority is to be given to, and
issuing an instruction based on the vector processing instruction to the vector processing means according to the determination contents and resource information of the vector processing means.
According to the ninth aspect of the invention, a computer readable memory which stores a control program for controlling a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, the control program comprising the steps of:
issuing a vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through a path connecting the CPUs to each other, and
comparing the issuing source CPU information contained in the vector processing instruction transferred and structure information regarding a vector pipeline of its own CPU to determine contents for processing for the vector processing instruction transferred.
According to the tenth aspect of the invention, a computer readable memory which stores a control program for controlling a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means,
the control program comprising the steps of:
divisionally setting the CPUs to be a master CPU for executing scalar processing, as well as issuing a vector processing instruction to other CPU and a slave CPU for receiving a vector processing instruction transferred from the master CPU to operate as a multi-vector pipeline in synchronization with a vector processing unit in the master CPU,
at the master CPU,
issuing the vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through the path, and
at the master CPU and the slave CPU
comparing the issuing source CPU information contained in the vector processing instruction transferred and master CPU information set at its own CPU, and
issuing, to the vector processing means, an instruction based on the vector processing instruction transferred when a comparison results in finding accord and invalidating the vector processing instruction when the comparison results in finding disaccord.
According to another aspect of the invention, a computer readable memory which stores a control program for controlling a shared memory type vector processing system including a plurality of CPUs sharing a main storage memory and each having scalar processing means and vector processing means, the control program comprising the steps of:
issuing a vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring the instruction to all the CPUs including its own CPU through a path connecting the CPUs to each other, and
storing the vector processing instruction transferred in a plurality of instruction stacks corresponding to the respective CPUs based on the issuing source CPU information to control instruction issuance based on the vector processing instruction according to priority of each of the plurality of instruction stacks and resource information of the vector processing means.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.